# A CMOS Replacement Integrated Circuit for a SiGe 802.11b Wireless LAN Transceiver

Li*, James, Myers and O*

### *University of Florida, Gainesville, FL32611 Intersil Corporation, 62B-017, 2041 Palm Bay Rd. NE, Palm Bay, FL 32905-3378

### Abstract — This paper describes a 2.4 GHz 0.25 micron CMOS RF transceiver chip that has the potential to replace a SiGe transceiver chip used in an 802.11b radio. The radio employs a traditional superheterodyne architecture. The RF transceiver chip features a low noise amplifier (LNA), followed by a down converter mixer on the receiver side. It also consists of an up converter mixer and a transmit amplifier on the transmitter side. The VCO is off-chip while the RF Phase Lock Loop (PLL) frequency synthesizer and LO buffers are on chip. The RF transceiver was originally built in a SiGe BiCMOS process and this paper focuses on the design of a CMOS RF transceiver that has the potential to replace the SiGe chip. The 802.11b radio with CMOS transceiver was tested along with the radio with SiGe transceiver. THe performance of CMOS radio transmitter matches that of SiGe radio. It exhibits RMS power of 13.1 dBm at antenna output while the SiGe radio transmitter has 13.2 dBm. CMOS radio receiver has sensitivity of -81 dBm at 11Mbps while the SiGe receiver has sensitivity of -84 dBm. Overall, the radio with CMOS transceiver consumes 6% more current than the one with SiGe chip.

### I. Introduction

IEEE 802.11b based Wireless Local Area Network (WLAN) systems have enjoyed robust growth over the past few years [1]. This paper describes a 2.4-GHz 0.25-µm CMOS RF transceiver chip that has the potential to replace an RF transceiver chip fabricated in a SiGe BiCMOS process currently used in PRISM II.5 802.11b radios. This lower cost RF CMOS transceiver can be used to implement a 802.11b radio which has comparable power consumption as radios using a SiGe transceiver, and which has the lowest power consumption among 802.11b radios using CMOS transceivers reported to date.

Fig. 1. An 802.11b WLAN Radio

The radio shown in Figure 1 employs a traditional superheterodyne architecture. On the receiver side, the antenna is routed to a ceramic band pass filter (BPF) which attenuates out of band signals as well as the 1.7 GHz image signal. The received signal then goes to the RF transceiver chip which converts the signal at an RF frequency of 2.400 to 2.484 GHz (ISM band) to an IF frequency of 374 MHz. An RF synthesizer is included in the IC with an off-chip VCO. On the transmitter side, the same RF transceiver converts the signal at 374 MHz to an RF frequency in the ISM band. A power amplifier (PA) then boosts the signal to around 18 dBm. A differential 374 MHz channel selection SAW filter follows the RF transceiver. A separate IF chip converts the received signal after the SAW to baseband (receive mode) or modulates the baseband transmit signal to IF (transmit mode). The baseband processor (BBP) implements the IEEE 802.11 CCK modulation. The MAC serves as a digital interface between the 11 Mbps data and computer/controller.

Contrary to the conventional wisdom, a superheterodyne WLAN transceiver usually consumes less power than a direct conversion transceiver. The main reason is that most direct conversion transceiver chips use differential design techniques to prevent LO leakage through the substrate, bond wires and package. The superheterodyne transceiver circuits, on the other hand, are mostly single-ended. Another reason is that, since the channel selection is performed by a SAW filter, the dynamic range of the subsequent IF and baseband circuits can be relaxed. On top of that, the extra circuitry associated with DC cancellation in direct conversion transceiver is avoided, resulting in both power and die area reduction. The image problem associated with a superheterodyne receiver can be tackled by careful frequency planning. If the image is located in a quiet band and is far away from carrier frequency, the front-end band pass filter and the tuned response of LNA render more than 50 dB of image rejection, obviating the need of an external image rejection filter. This means use of the superheterodyne architecture requires one external filter versus two external baluns typically needed for direct conversion radios. Because of these, fundamentally, the differences in PC board area and external component cost for the two radio architectures should be small.

Figure 1 also shows the components of the RF transceiver chip. The receiver chain features a low noise amplifier (LNA), followed by a down conversion mixer [2]. The transmit chain consists of an up conversion mixer and a transmit amplifier (TXA). The remaining circuitry comprises an RF Phase Locked Loop (PLL) frequency synthesizer and on-chip LO buffers: the LO signal is generated by an off-chip VCO and comes into the RF transceiver chip single endedly. It is converted to differential signal using an on-chip converter. This differential signal is then buffered through three source followers and amplified to drive the mixer switching cores in the Rx and Tx mixers as well as the clock of the prescaler.

Fig. 2. CMOS (Left) and SiGe (Right) Transmit Amplifiers

The CMOS transceiver IC is fabricated in a 0.25 µm foundry CMOS process. For low cost, MIM capacitor and high resistance resistor options are not used. Instead, capacitors are formed using the free MOS structure [3], while resistors are formed using the gate polysilicon layer. Most of the RF circuits in CMOS transceiver are implemented using the same topology and similar schematic as their SiGe counterparts. LNA's are single stage cascode amplifiers with inductive degeneration while the Rx mixers as well as Tx mixers are Gilbert type double balanced active mixers [2]. Figure 2 shows the schematic of CMOS and SiGe TXA's. CMOS TXA assumes a single stage, common source cascode configuration and the SiGe TXA is a simple one transistor common emitter amplifier. Usually the noise figure is not a huge concern in transmitter design so both TXA's are matched with an on-chip inductor at the input. The frequency synthesizer is an integer N charge pump PLL with a dual-modulus divide-by 32/33 prescaler. The loop filter is off-chip.

Fig. 3. Measured Transmitter Output Spectrum: Left, CMOS Radio; right, SiGe Radio

Figure 3 demonstrates the measured transmitter spectra of both CMOS and SiGe radios at maximum antenna output power of 13 dBm. Figure 4 shows the transmitter eye patterns at the same output power level. The transmitter chain in the CMOS IC performs as well as that in the SiGe chip. Figure 5 compares the measured receiver sensitivity of the two WLAN radios at 11 Mbps data rate. The CMOS and SiGe radios have Rx sensitivity of -81 dBm and -84 dBm respectively. Figure 6 shows the micro-photograph of the CMOS chip. The CMOS IC has a die area of 2.5 mm x 2.5 mm which is slightly smaller than that of the SiGe transceiver. It is also housed in the same 44 pin Micro Lead Frame (MLF) package so its pinout can be compatible.

Fig. 4. Measured transmitter eye pattern: 11 Mbps CCK signal: Left, CMOS radio; right, SiGe radio.

Fig. 5. Measured receiver sensitivity at 11 Mbps:

Left, CMOS Radio; right, SiGe Radio

Fig. 6. Chip micro-photograph of CMOS RF transceiver

Table 1 summarizes the RF and radio performance of the CMOS and SiGe radios. The performance of the two radios is close due to the robustness of superheterodyne radio design. The CMOS transceiver has slightly higher noise figure and lower power gain than the SiGe one. The loop bandwidth of the PLL frequency synthesizer is set to be 1 kHz. Phase noises of CMOS and SiGe PLL synthesizer are -81 dBc/Hz and -83 dBc/Hz at 10 kHz offset, respectively. The total current consumption of CMOS transceiver is 10 mA (Rx) or 15 mA (Tx) more than its SiGe counterpart. When the power consumption of the entire radio is considered, CMOS radio consumes less than 5% more current than that for the SiGe radio. The -81 dBm CMOS receiver sensitivity is 5 dB better than what's required by IEEE 802.11b standard. Previous experimental evaluation of slightly modified versions of stand alone LNA and mixer has shown that the gain and noise figure of 0.25-mm CMOS transceiver can be 23 dB and 4.0 dB at the same power consumption [2], demonstrating that CMOS radio receiver sensitivity can be further improved to match that of the SiGe radio.

### References

[1] Jim Paviol, Carl Andren, and John Fakatselis, "Wireless Local Area Networks," in Microwave and RF Handbook, CRC Press, 2001S. S.

[2] X. Li, T. Brogan, M. Esposito, B. Myers and K. O, IEEE Custom Integrated Circuits Conference, San Diego, pp. 531-534, 2001.

[3] C.-M. Hung, Y.-C. Ho, I-C. Wu, and K. K. O, IEEE Trans. Microwave Theory and Techniques, Vol. 46, No. 5, pp. 505-511, May 1998.